The present invention relates to microelectronic packages and more particularly to microelectronic packages such as semiconductor chip packages in which a plurality of semiconductor elements are stacked one on top of the other.
Semiconductor chips are commonly provided as individual, prepackaged units. In some unit designs, the semiconductor chip is mounted to a substrate or chip carrier, which is in turn mounted on a circuit panel, such as a printed circuit board. The circuit board usually has electrical conductors, normally referred to as traces extending in a horizontal direction parallel to the surface of the circuit board and terminals or other electrical conductive elements connected to the traces. The packaged chips are mounted so that the terminals disposed on each unit are electrically connected to contact pads or terminals of the circuit board. In this conventional arrangement, the theoretical minimum area of the circuit board must be at least equal to the aggregate areas of all the terminal-bearing surfaces of the individual prepackaged units. However, in practice, the circuit board must be somewhat larger than this. Thus, space issues often arise. Additionally, traces in these configurations must have significant length and impedance, so that appreciable time is required for propagation of signals along the traces and the speed of operation of the circuit is limited.
To alleviate these drawbacks, the “stacking” of units above one another in a common package is often employed. Essentially, in this type of design, the package itself has vertically extending conductors that are connected to the terminals of the circuit board. In turn, the individual chips within the package are connected to these vertically extending conductors. Because the thickness of a chip is substantially smaller than its horizontal dimensions, the internal conductors can be shorter than the traces on a circuit board that would be required to connect the same number of chips in a conventional arrangement. Examples of such stacked package designs are taught in U.S. Pat. Nos. 5,861,666; 5,198,888; 4,956,694; 6,072,233; and 6,268,649; and U.S. Patent Publication No. 2003/010711801; and pending patent application Ser. No. 11/291,398 filed Dec. 1, 2005, and patent application Ser. No. 60/923,953 filed Apr. 16, 2007, the disclosures of which are hereby incorporated by reference herein. Oftentimes, the vertically extending conductors are in the form of solid balls or the like, which connect the prepackaged units to each other and to the circuit board.
Despite the considerable efforts in the art towards development of stacked packages, still further improvements would be desirable.